Rubric: Proceedings - General Proceedings

VDE ITG (Ed.)

SMACD / PRIME 2021

International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design and

2021, 423 pages, 140 x 124 mm, Slimlinebox, CD-Rom
ISBN 978-3-8007-5588-2, e-book: ISBN 978-3-8007-5589-9
Personal VDE Members are entitled to a 10% discount on this title

Content Foreword

178.00 € CD-Rom 178.00 € e-book/PDF

SMACD 2021 – International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design.

The 2021 edition of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) was originally planned in Erfurt, Germany, but will be held virtually, as a forum devoted to modeling, simulation and synthesis for Analog, Mixed-signal, RF (AMS/RF) and multi-domain (nanoelectronics, biological, MEMS, optoelectronics, etc.) integrated circuits and systems.
Experiences with modeling, simulation and synthesis techniques including machine-learning and artificial intelligence in diverse application areas are also welcomed. Objective technologies include CMOS, beyond CMOS, and, Morethan-Moore such as MEMS, power devices, sensors, passives, etc. SMACD 2021 is Technically Co-sponsored by IEEE, IEEE CEDA and IEEE CAS. The conference proceedings will be submitted for inclusion in IEEExplore.

PRIME 2021 – 16th Conference on PhD Research in Microelectronics and Electronics
PRIME has been established over the recent years as an important conference where PhD students and postdocs with less than one year post-PhD experience can present their research results and network with experts from industry, academia and research. PRIME 2021 will feature conference program reflecting the wide spectrum of research topics in Microelectronics and Electronics, building bridges between various research fields. In addition to the technical sessions, opportunities for the conference attendees will be the keynote talks, workshops, social events and conference proceedings will be submitted for IEEE Xplorer.

VDE ITG – Informationstechnische Gesellschaft im VDE
Die VDE ITG ist als interdisziplinär arbeitende, wissenschaftliche Fachgesellschaft in das fachübergreifende Netzwerk des VDE eingebunden. Sie agiert als Schnittstelle für Experten der Informationstechnik (ITK) in Wirtschaft, Verwaltung, Lehre und Forschung. Ihre Mitglieder bündeln in enger internationaler Anbindung die deutsche Kompetenz im Bereich der ITK. Die VDE ITG fördert Forschung und Anwendung dieser Schlüsseltechnologie sowie deren effizienten Einsatz in den Bereichen Daten- und Kommunikationstechnik und -systeme, Umweltschutz, Medizin und Verkehr.

This conference proceeding contains the following papers, purchasable as PDF download with payment via credit card / PayPal:

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Qubit Gate Quality Loss Through Circuit Parasitics and Noise

Authors:

Geck, Lotte; van Waasen, Stefan

Modeling Power Supply Noise in RF SoCs

Authors:

Meier, Jonas; Menke, Florian; Wang, Lantao; Lauber, Tim; Wunderlich, Ralf; Heinen, Stefan

High-Performance Flexible and Printed Electronics Based on Inorganic Semiconducting Structures

Authors:

Dahiya, Abhishek Singh; Shakthivel, Dhayalan; Kumaresan, Yogeenth; Dahiya, Ravinder

Optimizing Neural Networks for Embedded Hardware

Authors:

Helms, Domenik; Amende, Karl; Bukhari, Saqib; de Graaff, Thies; Frickenstein, Alexander; Hafner, Frank; Hirscher, Tobias; Mantowsky, Sven; Schneider, Georg; Vemparala, Manoj-Rohit

The Essential Role of Procedural Approaches in Electronic Design Automation

Authors:

Marolt, Daniel; Scheible, Juergen; Jerke, Goeran; Marolt, Vinko

Trash or Treasure? Machine-learning based PCB layout anomaly detection with AnoPCB

Authors:

Franke, Henning; Kucera, Paul; Kuners, Julian; Reinhold, Tom; Grabmann, Martin; Maeder, Patrick; Seeland, Marco; Glaeser, Georg

A Deep Learning Toolbox for Analog Integrated Circuit Placement

Authors:

Gusmao, Antonio; Canelas, Antonio; Horta, Nuno; Lourenco, Nuno; Martins, Ricardo

A Differential Evolution based Methodology for Parameter Extraction of Behavioral Models of Electronic Components

Authors:

Alia, Gazmend; Buzo, Andi; Ludwig, Daniel; Maurer, Linus; Pelz, Georg

Machine Learning in the Analog Circuit Simulation Loop

Authors:

Tzenov, Petar; Sokar, Ahmed

Bringing Structure into Analog IC Placement with Relational Graph Convolutional Networks

Authors:

Gusmao, Antonio; Horta, Nuno; Lourenco, Nuno; Martins, Ricardo

Machine Learning in Charge: Automated Behavioral Modeling of Charge Pump Circuits

Authors:

Grabmann, Martin; Landrock, Christian; Glaeser, Georg

Frequency-Limited Reduction of RLCK Circuits via Second-Order Balanced Truncation

Authors:

Axelou, Olympia; Garyfallou, Dimitrios; Floros, George

A Mixed Time-Frequency RF Simulation Technique Based on Numerical Time-Slot Partitioning

Authors:

Oliveira, Jorge F.

Application of Asymmetric Crosstalk Harnessed Signaling on 3D Hexagonal Interconnect Arrays

Authors:

Iparraguirre, Daniel; Delgado-Frias, Jose

Adaptive Test Bench Generation, Simulation and Parameter Extraction for AMS Circuitry

Authors:

Meyer, Alexander; Weihs, Leon; Wunderlich, Ralf; Heinen, Stefan

Monitoring Analog Circuit Performance using Adaptive Filters and RSM-based Behavioral Models

Authors:

Taddiken, Maike; Paul, Steffen; Peters-Drolshagen, Dagmar

A Compact Model for Scalable MTJ Simulation

Authors:

Garcia-Redondo, Fernando; Prabhat, Pranay; Bhargava, Mudit; Dray, Cyrille

A Quantitive Analysis of the Recovery Effect in Batteries from Datasheets

Authors:

Bocca, Alberto; Chen, Yukai; Wang, Wenlong; Macii, Alberto; Macii, Enrico; Poncino, Massimo

A Phase Error Correction Algorithm for RF Energy Harvesters Using Two Antennas

Authors:

Guengoerdue, Ali Dogus; Erol, Didem; Caglar, Alican; Yelten, Mustafa Berke

Robust Design Methodology for RF LNA including Corner Analysis

Authors:

Martinez-Perez, Antonio D.; Aznar, Francisco; Royo, Guillermo; Martinez-Martinez, Pedro A.; Celma, Santiago

Event-Driven Modeling and Simulation of 5G NR-Band RF Transceiver in SystemVerilog

Authors:

Park, Chan Young; Kim, Jaeha

Sensitivity analysis in dynamic WPT systems based on non-intrusive stochastic methods

Authors:

Lagouanelle, Paul; Di Capua, Giulia; Femia, Nicola; Freschi, Fabio; Maffucci, Antonio; Pichon, Lionel; Ventre, Salvatore

Performance Analysis of IPT Systems for Electric Vehicles Dynamic Battery Charging

Authors:

Di Capua, Guilia; De Guglielmo, Luca; Femia, Nicola

Coil Geometry Modeling and Optimization for a Bidirectional Wireless Power Transfer System

Authors:

Nigsch, Simon; Kyburz, Falk; Schenk, Kurt

Impact of the Pad Geometry on System-Level Performance Indicators for IPT Systems in Electrical Vehicles

Authors:

Maffucci, Antonio; Ventre, Salvatore; Delgado Exposito, Alberto

A Probe Placement Method for Efficient Electromagnetic Attacks

Authors:

Jiang, Minmin; Pavlidis, Vasilis F.

Dealing with hierarchical partitioning in bottom-up design methodologies

Authors:

Passos, F.; Saraza-Canflanca, Pablo; Castro-Lopez, Rafael; Roca, Elisenda; Fernandez, Francisco V.

Modeling and Optimization of Supply Sensitivity for a Time-Domain Temperature Sensor

Authors:

Tan, Jun

Noise Performance in Current Mirror Circuit based on CNTFET and MOSFET

Authors:

Marani, Roberto; Perri, Anna Gina

A gm/ID Sizing Method for High-speed Multi-stage Operational Amplifiers with Feedforward-only Compensation

Authors:

Xie, Qixu; Shi, Guoyong; Ye, Yaoyao

Hybrid Capacitor-less LDO with Switched-Mode Dead-Zone Control

Authors:

Laleni, Nellie; Tsiougkos, Andreas; Pavlidis, Vasilis

Verilog-A model development of a DC–DC boost controller with autonomous optimization

Authors:

Severin, Davide; Capodivacca, Giovanni; Tchodjie Tchamabe, Bernard Blaise; Buzo, Andi; Diaconu, Cristian-Vasile

Analog Circuit Abstraction to SystemC-AMS Secured by Affine Forms

Authors:

Tarraf, Ahmad; Hedrich, Lars

Simulating the impact of Random Telegraph Noise on integrated circuits

Authors:

Saraza-Canflanca, Pablo; Camacho-Ruiz, Eros; Castro-Lopez, Rafael; Roca, Elisenda; Martin-Martinez, Javier; Rodriguez, Rosana; Nafria, Montserrat; Fernandez, Francisco V.

Connecting Energy Storages from Tool Independent, Signal-flow Oriented FMUs

Authors:

Ehlert, Meik; Michael, Jan; Henke, Christian; Traechtler, Ansgar; Kalla, Matthias; Bagaber, Bakr; Ponick, Bernd; Mertens, Axel

Adaptive Simulation with HDL Control Module for Frequency Converting Circuits

Authors:

Tibenszky, Zoltan; Kreissig, Martin; Carta, Corrado; Ellinger, Frank

Step Size Determination Approach for Aging Simulations in Analog ICs

Authors:

Afacan, Engin

Schematic Generation of Programmable Analog Neural Networks for Signal Proccessing

Authors:

Aul, Florian; Katsaouni, Nikoletta; Krischker, Lukas; Schmalhofer, Sascha; Schulz, Marcel H.; Hedrich, Lars

Generators, Templates, and Code Generation for Flexible Automation of Array-Style Layouts

Authors:

Prautsch, Benjamin; Wittmannm, Reimund; Eichler, Uwe; Hatnik, Uwe; Lienig, Jens

Improvement of Simulation-Based Analog Circuit Sizing using Design-Space Transformation

Authors:

Schweikardt, Matthias; Scheible, Juergen

Machine Learning Based Procedural Circuit Sizing and DC Operating Point Prediction

Authors:

Uhlmann, Yannick; Essich, Michael; Schweikardt, Matthias; Scheible, Juergen; Curio, Cristobal

Surrogate-Assisted Multi-objective Differential Evolution based on Gaussian Process for Analog Circuit Synthesis

Authors:

Yin, Sen; Hu, Wenfei; Wang, Ruitao; Wang, Zhikai; Zhang, Jian; Wang, Yan

A fast Structural Synthesis Algorithm for Op-Amps based on Multi-Threading Strategies

Authors:

Abel, Inga; Kowalsky, Clara; Graeb, Helmut

An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization

Authors:

Martins, Ricardo; Gusmao, Antonio; Canelas, Antonio; Passos, Fabio; Lourenco, Nuno; Horta, Nuno

An Efficient Modeling Approach for Large Ring Oscillator Based Ising Machines

Authors:

Graber, Markus; Angeli, Nico; Hofmann, Klaus

The Merging Technique to Simulate Synchronization Mode of Coupled Oscillators

Authors:

Gourary, Mark M.; Rusakov, Sergey G.

RTL Implementation of MCMC-based Constraints Solver

Authors:

Ahmed, Moemen; Ahmed, Youssef; Nagy, Younan; Adbel-Rahman, Manar; Salah, Khaled; El-Kharashi, M. Watheq; Khan, Ayub

A study of SRAM PUFs reliability using the Static Noise Margin

Authors:

Camacho-Ruiz, Eros; Saraza-Canflanca, Pablo; Castro-Lopez, Rafael; Roca, Elisenda; Brox, Piedad; Fernandez, Francisco V.

Design and Optimization of a Control Algorithm for a Digital Low-Dropout Regulator in System-on-Chip Applications

Authors:

Ohse, Benedikt; Tan, Jun

A Differential Public PUF Design for Lightweight Authentication

Authors:

Duan, Shengyu; Sai, Gaole

Organic Transistor Parameter Estimation and Accurate Modeling for Process Optimization

Authors:

Liguori, Rosalba; Licciardo, Gian Domenico; Di Benedetto, Luigi

Bias Temperature Instability Characterization and Modeling for 0.18um CMOS Under Extreme Thermal Stress Conditions

Authors:

Tran, Yen; Nomura, Toshihiro; Cherchali, Mohamed Salim; Tassin, Claire; Deval, Yann; Maneux, Cristell

Run-Time Adaptive Hardware Accelerator for Convolutional Neural Networks

Authors:

Sestito, Cristian; Spagnolo, Fanny; Corsonello, Pasquale; Perri, Stefania

Design and Analysis of a Leading One Detectorbased Approximate Multiplier on FPGA

Authors:

Scarfone, Salvatore; Frustaci, Fabio; Perri, Stefania

Extending a RISC-V core with an AES hardware accelerator to meet IOT constraints

Authors:

Zgheib, Anthony; Potin, Olivier; Rigaud, Jean-Baptiste; Dutertre, Jean-Max

Memristive Logic-in-Memory Implementations: A Comparison

Authors:

Inglese, Pietro; Vatajelu, Elena Ioana; Di Natale, Giorgio

A 12-bit 100 MHz SAR ADC in 110-nm CMOS for MAPSs

Authors:

Tedesco, Silvia

A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter

Authors:

Be, Gabriele; Mercandelli, Mario; Bertulessi, Luca

A low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process

Authors:

Ricci, Luca; Bertulessi, Luca; Bonfanti, Andrea

A 2GS/s 10-bit Time-Interleaved Capacitive DAC for Self-Interference-Cancellation Application

Authors:

Abedinkhan Eslami, Mazyar; Manstretta, Danilo; Castello, Rinaldo

Implementation of a Low Power Decimation Filter in a 180 nm HV-CMOS Technology for a Neural Recording Front-End

Authors:

Sporer, Markus; Graber, Nicolas; Moll, Steffen; Reich, Stefan; Ortmanns, Maurits

Analog Baseband Filter and Variable-gain Amplifier for Automotive Radars in 22 nm FD-SOI CMOS

Authors:

Seidel, Andres; Li, Songhui; Szilagyi, Laszlo; Carta, Corrado; Wagner, Jens; Ellinger, Frank

A Highly Linear High-Voltage Compliant Current Output Stage for Arbitrary Waveform Generation

Authors:

Schwarze, Felix; Protze, Florian; Matthus, Christian; Ellinger, Frank

A RISC-V-based System on Chip for High-Speed Control in Safety-Critical 650 V GaN-Applications

Authors:

Richter, Mike; Luedecke, Andre; Lee, Yoon-Cue; Stanitzki, Alexander; Utz, Alexander; Grau, Guenter; Kappert, Holger; Kokozinski, Rainer

An Approach to Online Wear Out Monitoring of PCB Interconnects in Safety-Critical Systems

Authors:

Yazdani, Saeid; Wolz, Werner; Engelhardt, Rainer; Schott, Christian; Heinkel, Ulrich; Kriesten, Daniel

Experimental Investigation of Dielectric Loss Induced Noise in Charge Detection Systems for Cosmic Dust

Authors:

Kelz, Sebastian; Groezing, Markus; Berroth, Manfred

Generalized comparison of the accessible emission limits of flash- and scanning LiDAR-systems

Authors:

Burkard, Roman; Viga, Reinhard; Ruskowski, Jennifer; Grabmaier, Anton

A Mixed-Precision Binary Neural Network Architecture for Touch Modality Classification

Authors:

Younes, Hamoud; Ibrahim, Ali; Rizk, Mostafa; Valle, Maurizio

A CMOS SPAD pixel with an integrated mixed-signal TDC

Authors:

Moreno, Sergio; Moro, Victor; Dieguez, Angel

Germanium – InGaZnO heterostructured thinfilm phototransistor with high IR photoresponse

Authors:

Ferhati, Hichem; Djeffal, Faycal; Bendjerad, A.

Integrated Hysteretic Controlled Regulating Buck Converter with Capacitively Coupled Bootstrapping

Authors:

Galea, Francarl; Casha, Owen; Grech, Ivan; Gatt, Edward; Micallef, Joseph

Single-Inductor Dual-Output Buck Converter with Charge Recycling

Authors:

Ozanoglu, Kemal; Dundar, Gunhan

Design of an integrated Maximum Power Point Boost Converter for PV Submodules

Authors:

Weihs, Leon; Hanhart, Michael; Rolff, Leo; Wunderlich, Ralf; Heinen, Stefan

Design of a High PSRR Multistage LDO with On-Chip Output Capacitor

Authors:

Zoche, Jonas; Hanhart, Michael; Grobe, Jan; Weihs, Leon; Rolff, Leo; Wunderlich, Ralf; Heinen, Stefan

Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits

Authors:

Scaletti, Lorenzo; Parisi, Angelo; Bertulessi, Luca

Entropy Analysis of RO-based Physically Unclonable Functions

Authors:

Diez-Senorans, Guillermo; Garcia-Bosque, Miguel; Sanchez-Azqueta, Carlos; Celma, Santiago

On the Behavior of a Wide Set of Oscillators: PUFs or TRNGs?

Authors:

Garcia-Bosque, Miguel; Naya, Abel; Diez-Senorans, Guillermo; Sanchez-Azqueta, Carlos; Celma, Santiago

A 55 MHz Integrated Crystal Oscillator with Chirp Injection Using a 28-nm Technology

Authors:

Wang, Lantao; Arnold, Adrian; Meier, Jonas; Scholl, Markus; Wunderlich, Ralf; Heinen, Stefan

A low-power 26.56-GHz LC-based DCO for multi-gigabit communication systems

Authors:

Jimenez-Fernandez, Pablo; Guerra, Oscar; del Rio, Rocio; Rodriguez-Perez, Alberto; Prefasi, Enrique

A Wide-Tuning-Range 55 GHz CMOS VCO on 22 nm FD-SOI Technology

Authors:

Tibenszky, Zoltan; Carta, Corrado; Ellinger, Frank

A Fully Integrated 28 GHz Class-J Doherty Power Amplifier in 130 nm BiCMOS

Authors:

Veni, Simone; Caruso, Michele; Seebacher, David; Neviani, Andrea; Bevilacqua, Andrea

A Scalable CPW Circuit Model in Advanced CMOS Technologies for mm-Wave frequencies

Authors:

Guizan, Carla Moran; Baumgartner, Peter; Heinen, Stefan

A Sub-1muA Low-PowerLow-NoiseAmplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential Signals

Authors:

Vieira, Rafael; Martins, Ricardo; Horta, Nuno; Lourenco, Nuno; Povoa, Ricardo

Transistor Downscaling toward Ultra-Low-Power, sub-100 mum2 and sub-Hz Oscillators

Authors:

Barbruni, Gian Luca; Bielli, Chiara; Demarchi, Danilo; Carrara, Sandro

Electronic solution to compensate the effects of the temperature and the humidity on the measurements of a capacitive sensor dedicated to an injection insulin pen

Authors:

Joly, Sylvain; Lepple-Wienhues, Albrecht; Dehollain, Catherine

A First Order-Curvature Compensation 5ppm/degC Low-Voltage & High PSR 65nm-CMOS Bandgap Reference with one-point 4-bits Trimming Resistor

Authors:

Barteselli, Edoardo; Sant, Luca; Gaggl, Richard; Baschirotto, Andrea

Resource Efficient Sub-VT Level Shifter Circuit Design Using a Hybrid Topology in 28 nm

Authors:

Chatterjee, Saikat; Rueckert, Ulrich

VDE ITG (Ed.)

SMACD / PRIME 2021

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