Verilog-A model development of a DC–DC boost controller with autonomous optimization

Abstract:
Simulation time of wide schematic is often the rootcause of time-to-market worsening, especially during the design verification of large switchable circuit. To speed CPU-time up equivalent models can be used in place of the original modules, but they are often created for a specific project and requires a manual tuning of the specification. This contribution provides a methodology to develop Verilog-A equivalent models whose implementation is general, maintaining the physical coherence and parameterizing the internal properties. This large set of parameters is tuned with an autonomous Artificial Intelligence algorithm (GDE3) so that to achieve the required Mean Percentage Error (MPE) but reducing the human effort in optimization from some weeks down to a couple of days. The entire methodology has been applied to a DC–DC boost converter, decreasing the simulation time of an order of magnitude.