Modeling Power Supply Noise in RF SoCs

Abstract:
With rising integration densities and design complexities, the verification effort of modern Systems-on-Chip is rising even faster. Additionally, with the shift towards digitalcentric circuits in smaller process nodes, supply noise has become a critical factor as it can degrade the performance of the remaining analog and RF components drastically. This paper provides an overview on recent advances in modeling power supply noise on block level. Considerations to transfer these approaches for simulating noise on system level are highlighted. An All-Digital PLL SoC is used as an example to showcase the insights that can be derived even when using simple models. The position and causes for spurs arising due to coupling on the power supply lines are investigated, giving designers a guideline on where to focus their optimization efforts.