A low-power 26.56-GHz LC-based DCO for multi-gigabit communication systems

Abstract:
A voltage controlled oscillator (VCO) is one of the key building blocks in RF transceivers. By means of a Phase- Locked Loop (PLL) that controls the VCO, a clock signal at the desired frequency can be generated. Communications systems for multi-gigabit applications require high accuracy in the clock signal, so low phase noise of the VCO must be achieved. This paper presents the design of a 26.56-GHz digitally controlled VCO (DCO). The circuit is powered at 1.2 V and consumes 1.94 mW. Post-layout simulations based on a TSMC 65-nm CMOS RF process show a phase noise of -123.3 dBc/Hz at 10-MHz offset. By modelling the noise contributions of the digital PLL, a 242.84- fs rms jitter (integrated from 100 kHz to 100 MHz) has been estimated. The proposed DCO exhibits a FoM of -188.6 dBc/Hz at 1-MHz offset frequency.