Digitally Programmable Potentiometer Multistage Architecture with Switch Independent Linearity
Conference: SMACD / PRIME 2021 - International Conference on SMACD and 16th Conference on PRIME
07/19/2021 - 07/22/2021 at online
Proceedings: SMACD / PRIME 2021
Pages: 4Language: englishTyp: PDF
Authors:
Ilie, Giorgiana-Catalina (Power Solutions Group – ON Semiconductor Univerisity “Politehnica” of Bucharest, Bucharest, Romania)
Tudoran, Cristian; Neagoe, Otilia (formerly of Power Solutions Group – ON Semiconductor, Bucharest, Romania)
Pristavu, Gheorghe; Brezeanu, Gheorghe (Dept. of Electrical Devices and Circuits University “Politehnica” of Bucharest, Bucharest, Romania)
Abstract:
This paper describes a multistage architecture for high resolution digitally programmable potentiometers. Its linearity characteristics dependence on switch’s on-resistance is highly diminished. The proposed topology was implemented in a 0.18 µm CMOS process and used in fabricating an 8-bit resolution digital potentiometer with I2C interface. The maximum measured values for its non-linearity errors are 0.25LSB for INL and 0.1LSB for DNL. A theoretical model for determining the non-linearity errors was developed for this architecture. It is proven that the linearity characteristics of the potentiometer are not affected by switches on-resistances. Moreover, the experimental non-linearity error values are attributed to deviations in unit resistances caused by process variations.