Rubrik: Proceedings - Allgemeine Proceedings
DVCon Europe 2024
größer

DVCon Europe (Hrsg.)

DVCon Europe 2024

Design and Verification Conference and Exhibition October 15 – 16, 2024 in Munich, Germany

2024, 74 Seiten, 140 x 124 mm, Slimlinebox, CD-Rom
ISBN 978-3-8007-6438-9, E-Book: ISBN 978-3-8007-6439-6
Persönliche VDE-Mitglieder erhalten auf diesen Titel 10% Rabatt

Inhaltsverzeichnis Vorwort

The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. Sponsored by Accellera Systems Initiative, DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.

General topic areas on Electronic System Level (ESL), Verification & Validation, Analog/Mixed-Signal, IP reuse, Design Automation, and Low Power design and verification, will be highlighted in tutorials, papers, and poster sessions.

With a highly technical focus on System and IC design, verification, and integration, DVCon Europe is a very practical and industry-focused conference on EDA standards and standardization.
DVCon Europe organizes technical workshops and tutorials on emerging EDA and IP standards, with highly educational content. Experts in the industry share on topics like UVM, SystemC and IP-XACT, with the fundamental concepts and practical usage of these standards explained, including examples and demonstrations.
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1

Virtual Prototyping Framework for Pixel Detector Electronics in High Energy Physics

Autoren: Brambilla, Francesco E.; Ceresa, Davide; Dhaliwal, Jashandeep; Esposito, Stefano; Kloukinas, Kostas; Prinzie, Jeffrey
2

Formal RTL Sign-off with Abstract Models

Autoren: Deutschmann, Lucas; Ayoub, Osama; Batthineni, Rohith; Schwarz, Michael; Ludwig, Tobias; Stoffel, Dominik; Kunz, Wolfgang
3

A Roundtrip: From System Requirements to Circuit Variations and Back

Autoren: Kwasigroch, Soeren; Theobald, Nicolas; Koch, Johannes; Grimm, Christoph
4

OpenCar: A SysML v2 Modeling Framework for Early Analysis of BoardNet Architectures

Autoren: Post, Sebastian; Koch, Johannes; Bevrnja, Aida; Grimm, Christoph
5

Automating the Use of State-Space Representations in Mixed-Signal IC Design and Verification

Autoren: Stilgenbauer, Francesco; De Ferrari, Matteo; Meroni, Christiano; Ridino, Giuseppe; Macario, Christian; Crovetti, Paolo Stefano; Bonizzoni, Edoardo; Malcovati, Piero
6

Who checks the checkers? Automatically finding bugs in C-to-RTL formal equivalence checkers

Autoren: Pardalos, Michalis; Donaldson, Alastair F.; Morini, Emiliano; Pozzi, Laura; Wickerson, John
7

A Novel Approach in Proving Unreachable Paths in Hardware-dependent Software

Autoren: Olmos, Bryan; Kunz, Wolfgang; Lettnin, Djones
8

Trustworthiness Evaluation of Deep Learning Accelerators Using UVM-based Verification with Error Injection

Autoren: Aboudeif, Randa; Awaad, Tasneem A.; AbdElsalam, Mohamed; Ismail, Yehea
9

Enhanced VLSI Assertion Generation: Conforming to High-Level Specifications and Reducing LLM Hallucinations with RAG

Autoren: Quddus, Hafiz Abdul; Hossain, Md Sanowar; Cevahir, Ziya; Jesser, Alexander; Amin, Md Nur
10

Securing Silicon: A Scalable, Platform-independent Hardware Security Verification Methodology

Autoren: Faisal, Muhammad Abdullah Al; Nagar, Jaimini; Dworzak, Thorsten; Simon, Sebastian; Heinkel, Ulrich; Lettnin, Djones
11

Reliable and Real-Time Anomaly Detection for Safety-Relevant Systems

Autoren: Heermann, Hagen; Koch, Johannes; Grimm, Christoph