A Phase-Locked Loop (PLL) based Strategy for Accurate Blanking Times in Bridgeless Totem-Pole PFCs

Inhalt:
Bridgeless totem-pole Power Factor Correction (PFC) circuits experience current distortion around the ac voltage zero-crossings due to flaws in the synchronization with the grid and the reverse recovery phenomenon in the power devices switching at grid frequency, combined with the fast current change trough the active power device switching at high frequency. Blanking times and soft-start strategies are used to attenuate these effects, respectively. The incorporation of blanking intervals within the gate signals for the line frequency switching power devices is achieved by comparing of the measured grid voltage and a predetermined threshold level. This method facilitates the turn-off of the power device during each semi-cycle of the ac voltage before the occurrence of the zero-crossing event. However, grid voltage disturbances and a static threshold level result in suboptimal blanking times under changing operation conditions. A Phase-Locked Loop (PLL) is used not only to estimate the electrical grid angle and generating the instantaneous reference current but also for rejecting noise around the zero crossings. However, integrating a PLL within the multiloop controller implemented in a microcontroller (muC) is challenging since the computational burden associated with PLLs is relatively high compared to zerocrossing detector (ZCD) based controllers. This manuscript focuses on this issue and provides insights into PLL implementations on the TI C2000 muC.