Challenges in Scaling SiC Single-Chip Measurements to Corresponding Power Modules

Inhalt:
To experimentally model the electrical behaviour of high-power modules, it is common practice to scale based on measurements from a single chip. The traditional approach involves scaling commutation loop inductance L (σ) to align the overshoot voltage between the scaled single chip and the module. Nevertheless, scaling only L (σ) often is not enough to match transient behaviours. This is due to the impact of parasitic parameters like common source inductance L (com) on transient behaviours. In this paper, a new scaling method is introduced, which takes additional parameters into consideration, offering a more comprehensive approach to aligning the transient behaviour.