Influence of the Gate Voltage during On-Time on the Power Cycling Capability of SiC MOSFETs
Konferenz: PCIM Europe 2024 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
11.06.2024-13.06.2024 in Nürnberg, Germany
doi:10.30420/566262274
Tagungsband: PCIM Europe 2024
Seiten: 9Sprache: EnglischTyp: PDF
Autoren:
Heimler, Patrick; Schwabe, Christian; Thoenelt, Nick; Gesell, Soeren; Lutz, Josef; Basler, Thomas
Inhalt:
In this work, the power cycling capability of SiC MOSFETs in the TO-247 package from three different manufacturers (chip structure: planar, single trench and double trench) was investigated at different positive gate voltages during on-time (VGS,on = + 8 V … + 20 V). It was found that the TCP (temperature compensation point) of the RDS(ON) in a gate voltage range of 10 V to14 V is depending on the chip technology. The test results show that the power cycling capability decreases strongly when using gate voltages below the TCP. Therefore, the choice of the gate voltage should be considered for the test conditions. The cause of end-of-life failure is an increase in forward voltage by 5 %, resulting from distinct bond wire degradation.