Design Challenges and Considerations for Gate Drivers of SiC MOSFETS and their Testing

Inhalt:
The testing of SiC gate drivers involves various parameters, including turn-on and turn-off delay times, switching losses, and short circuit protection. These tests help to ensure that the SiC-based power electronics devices are operating efficiently, reliably, and safely. Silicon carbide typically has high dv/dt and di/dt and is accompanied with high-speed switching operations. This can cause EMI noise and stability issues. Gate drivers need to be immune to these noise problems. While designing high performance gate drive circuits, some of the unique characteristics of SiC, GaN MOSFETs like transconductance and negative gate voltage to fully discharge the gate are very important. Dynamic characteristics such as on−resistance, gate charge (Miller plateau) and over−current protection are also of high impact. When designing gate drivers for silicon carbide (SiC) power MOSFETs, it is crucial to consider the negative impacts caused by parasitic inductance in the gate loop. These effects may include false turn-on, gate overstress, and decreased switching speed. This paper talks about ways of testing driver parameters using oscilloscope and signal generator, which helps in signal visualization and accurate debugging.