The Impact of Different Test Methodologies on Short-Circuit Ruggedness of SiC MOSFETs

Inhalt:
This paper presents experimental results on 750 V and 1200 V SiC MOSFETs stressed under short-circuit (SC) type I conditions using two different test methods: incremental SC pulses until failure and a single SC pulse to failure. These two methods result in different values for short-circuit withstand time (tSCWT). TCAD simulations confirm that, depending on technology and test conditions, turn-off energy and device degradation are the main causes for the measured tSCWT difference. Moreover, tSCWT is also dependent on device-to-device threshold voltage (Vth) variations, the external gate resistance (RG), and the power loop stray inductance (Lstray). The disparity between tSCWT when extracted according to either the AQG 324 or JEDEC 24-9 standards is also thoroughly discussed.