Aging of SiC MOSFETS Through Multistep Voltage Gate Switching Stress

Inhalt:
It is known that SiC MOSFETS experience parameter drifts after being subjected to repeated switching events. Multiple accelerated test results have been published on MOSFETS from different type and vendors, and prediction models established out of the results of those tests. The commonality of the tests presented hitherto is that they use one or two voltage levels at the gate to stress the chip. When it comes to multi-chip modules however, it is known that the gate-source voltage at each chip is seldom a strictly bipolar waveform. For the purpose of understanding whether a multistep voltage waveform is more or less benevolent to the parameter drift than the classical bipolar voltages, a new investigation with a strictly defined 4-voltage step waveform was used. The results of the investigation for these chips show that the drifts remain within acceptable limits and bipolar based models seem to overpredict the drifts observed under more realistic operating conditions.