Design of a Low Cost Over Temperature Detector Using the Internal Gate Resistance as TSEP

Inhalt:
The junction temperature of a power transistor is an important parameter for safe operation. The accurate and timely detection of abnormal temperature conditions is required to protect the device. Recently, an Over-Temperature Detection (OTD) method via internal and emulated gate resistance was proposed, validated and tested. A precision of ±4.2deg C was achieved in static operation. The precision was also evaluated in low voltage and current conditions. The presence of additional noise decreased the precision to ±7.4deg C. This paper investigates the origin of this noise and proposes countermeasures to increase noise immunity. As a result, a detection precision under ±2deg C was achieved in both static and power operation. Additional robustness tests were performed under varying current and voltage conditions. Detection during the on-time is sensitive to the current with a drift of +3deg C at half-nominal current. During the OFF-time, the detection is robust regarding both the current and the voltage, if the voltage is above 300V.