Avalanche Robustness of SiC MOSFETs in Parallel Connections

Inhalt:
In this paper, the avalanche robustness of SiC MOSFETs in parallel configurations of two devices was investigated. Device parameter deviations of breakdown voltage VBD are decisive for the development of current-sharing imbalances during the avalanche event. We study the extent to which these deviations affect the robustness of the overall parallel configuration, and in a comparison with single-device robustness, the extent to which derating needs to be considered. The investigations were carried out using a range of inductance values and corresponding critical avalanche times and energies.