Improved Short Circuit Ruggedness by Optimization of Sidewall P-type Pillar Ratio for Trench SiC-MOSFET Fabricated by Multiple Tilted Ion Implantation into Trench Sidewalls
Konferenz: PCIM Europe 2023 - International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management
09.05.2023-11.05.2023 in Nürnberg, Germany
doi:10.30420/566091022
Tagungsband: PCIM Europe 2023
Seiten: 5Sprache: EnglischTyp: PDF
Autoren:
Fukui, Yutaka; Adachi, Kohei; Honda, Shigeto; Kagawa, Yasuhiro; Furukawa, Akihiko (Power Device Works, Mitsubishi Electric Corp., Japan)
Sugawara, Katsutoshi; Hino, Shiro; Nishikawa, Kazuyasu (Advanced Technology R&D Center, Mitsubishi Electric Corp., Japan)
Inhalt:
We have developed a unique trench gate SiC-MOSFET, by applying bottom p-well (BPW), sidewall p-type pillar (SP) to be grounded to BPW, and JFET doping (JD) structures. The influence of the SP ratio (rSP), namely SP area / sidewall area, on major characteristics of the MOSFET was investigated. We have confirmed that higher rSP leads to lower loss during turn-off (Eoff) and higher loss during turn-on (Eon). By optimized rSP, excellent performance with short circuit withstanding time (tsc) of 2.2 mus was demonstrated with specific on-resistance (Ron,sp) as low as 2.2 mOmegacm2. We confirmed that increasing rSP brings improved tsc and slight increase of DC loss without increase of AC loss. The trade-off between DC/AC losses and tsc are adjustable by designing rSP, according to the requirement of the applications' needs.