A research on thermal resistance simulation analysis for thermal test chip
Konferenz: EEI 2022 - 4th International Conference on Electronic Engineering and Informatics
24.06.2022 - 26.06.2022 in Guiyang, China
Tagungsband: EEI 2022
Seiten: 5Sprache: EnglischTyp: PDF
Autoren:
Cai, Jiawei; Lv, Xiaorui; Huang, Yingzhuo; Lin, Pengrong; Yao, Quanbin (Beijing Microelectronics Technology Institute, Beijing, China)
Inhalt:
The semiconductor industry is developing rapidly in the direction of high integration and small size. Subsequently, the chip will face problems such as thermal failure under high heat flux density and enhanced thermal coupling of multiple heat sources. Therefore, it is particularly important to study the heat dissipation characteristics of chip packaging. Junction-to-case thermal resistance is one of the most important thermal performance parameters for measuring chip packaging. This paper designed a thermal test chip for package thermal resistance evaluation. In this work, the principle and design method of thermal test chip are introduced in detail, At the same time, the thermal test chip is simulated to obtain the main factors affecting the thermal resistance of the chip package. The simulation results indicate that this thermal resistance simulation analysis method has significant value.