Optimization of thermal performance of top-side cooled discrete power semiconductors

Inhalt:
Recent developments in power packaging technologies have resulted in the market introduction of Top- Side Cooled (TSC) discretes that house both silicon and wide-bandgap devices. Such packages address the application area of relatively low power (some tens of kilowatts), low voltage (kilovolt) applications characterised with very robust operation, elevated switching frequencies, flexible form factors and traditionally low-cost designs. This paper positions these packages with regards to traditional discretes and power modules with respect to capacity of thermal transfer to the heatsink and parasitics in the commutation cell. The experimental data presented here indicates that the TSC packages rival the per-die thermal resistance of low power modules, while the commutation loop parasitics are several times smaller than those for modules and classical surface-mount devices. This is attributed to the segregation of functions employed by TSC devices, permitting to physically separate the current conduction from the heat transport, whereby both of these functions can be optimised independently. Finally, the know-how obtained during the experimental set up in the use of TSC is also summarised and formulated as recommendations for thermal interfaces when using TSC packages.