Transfer IV and Threshold Voltage Drift of GaN and SiC Cascode Discrete Devices Under Gate Bias Stress

Inhalt:
Gallium Nitride (GaN) and Silicon Carbide (SiC) power cascode devices take advantage of a low-voltage enhancement-mode Silicon power MOSFET coupled with a high-voltage depletion-mode GaN HEMT or SiC JFET to realize high switching frequencies with the intention of avoiding charge trapping and threshold voltage drift in the gate oxide traps of enhancement-mode SiC MOSFETs. Nevertheless, in this paper it will be shown that SiC and GaN cascodes will also suffer from the gate threshold voltage drift when subject to significant electrothermal stress. This is due to charge trapping and the impact of additional leakage current in the high-voltage device and it can lead to permanent degradations.