Balancing the Switching Losses of Paralleled SiC MOSFETs Using an Intelligent Gate Driver

Inhalt:
This paper presents an intelligent gate driver for paralleled silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). Commercial gate drivers often slow down the switching processes with a relatively large gate resistance to compensate for the unbalanced losses of paralleled MOSFETs. Using the proposed driver topology, it is possible to individually delay the gate signals in a picosecond range to balance unevenly distributed switching losses of paralleled SiC MOSFETs. Therefore, it enables balancing the switching losses of several MOSFETs even at low gate resistances and, thus, exploits the full potential of SiC-MOSFET technology. The evenly distributed losses prevent a derating of the power module.