A Closed-Loop Power-Hardware-in-the-Loop Testbed for Low Voltage Modular Multilevel Converter Design Validation

Inhalt:
This paper shows the implementation of a closed-loop Power-Hardware-in-the-Loop (PHIL) testbed for the validation of a low voltage Modular Multilevel Converter (MMC) design with its advantages, enhancing the test and fault coverage significantly. At first, the usefulness of designing a low voltage MMC for laboratory experiments will be described. Then, the difficulties of testing such a converter with its test cases will be shown, presenting the solution utilizing a Real-Time Simulator (RTS) and a power amplifier to create a closed-loop PHIL testbed. Experimental results will then be presented to show the benefits of such closed-loop tests regarding the early test of MMC Commutation Cell (CC) prototypes and the controller validation. It also shows the stability constraints of a closed-loop test as a result of the power amplifier dynamics.