Time-dependent reliability of ultra-scaled CMOS devices and its impact on circuit performance

Inhalt:
Technology scaling has enabled increased speed, lower energy consumption and lower die cost. However, new reliability issues appear in these deep sub-micron technologies. The aging of devices during circuit operation will have to be considered during the circuit design phase, so that models that represent the modified behaviour of devices will be needed. In this work, the wear-out of the gate dielectric of MOS devices during electrical stress and its impact on the performance of devices and circuits are addressed. As an example of gate degradation impact on circuits, the wear-out effects in an inverter have been studied.