Hyperbolic Segmentation of Gate Driver Output Transistors for a Clean Switching of 650V GaN HEMTs Half Bridges

Konferenz: CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems
12.03.2024-14.03.2024 in Düsseldorf, Germany

Tagungsband: ETG-Fb. 173: CIPS 2024

Seiten: 5Sprache: EnglischTyp: PDF

Autoren:
Fiori, Franco (Politecnico di Torino, Torino, Italy)
Nuebling, Marcus; Klotz, Frank (Infineon Technologies, Munich, Germany)

Inhalt:
This paper deals with the mitigation of the overvoltages and the high frequency oscillations resulting from the fast switching of high voltage e-mode GaN HEMTs. The investigation is carried out referring to a half bridge including the power transistors package parasitics and the printed circuit boards stray inductances. The impact of the gate drivers strength on the above mentioned quantities is evaluated through time domain analysis by changing the width of the transistors composing the gate driver output stage. A criterion to perform the partitioning of such transistors that allow for a fine control of overvoltages and ringing is proposed, then used to design a segmented gate driver.