Substantial increase of power cycling capability of SiC MOSFETs after preconditioning

Konferenz: CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems
12.03.2024-14.03.2024 in Düsseldorf, Germany

Tagungsband: ETG-Fb. 173: CIPS 2024

Seiten: 8Sprache: EnglischTyp: PDF

Autoren:
Kempiak, Carsten; Lindemann, Andreas (Otto-von-Guericke-University, Magdeburg, Germany)

Inhalt:
Power cycling (P/C) tests are an established routine in the qualification process of power electronic devices. New challenges however evolve from the application to wide band gap devices: In case of SiC MOSFETs, the threshold voltage Vth is continuously shifting during the test execution affecting the on-state resistance RDS;on and thus the induced thermomechanical stress as well as a reliable failure indication, while the impact on P/C lifetime is yet unknown. Within this study a basic physical understanding of the causes of parasitic drift effects of SiC MOSFETs is briefly summarised and consequently, a preconditioning procedure is presented which enables to successfully suppress such parasitic drift effects during the subsequently performed P/C test. This way, their impact on lifetime can be investigated quantitatively for the first time. Initial experimental results indicate a substantial influence.