Influence of VDS Bias on SiC MOSFET Dynamic Gate Stress
Konferenz: CIPS 2024 - 13th International Conference on Integrated Power Electronics Systems
12.03.2024-14.03.2024 in Düsseldorf, Germany
Tagungsband: ETG-Fb. 173: CIPS 2024
Seiten: 5Sprache: EnglischTyp: PDF
Autoren:
Gebhardt, Mathias; Lieser, Gabriel (SET GmbH, NI, Wangen im Allgäu, Germany)
Inhalt:
Silicon carbide power semiconductors are commonly used for new designs. While the reliability of silicon power semiconductors is well understood silicon carbide power semiconductors show additional effects. One is the drift of the gate-source threshold voltage caused by gate switching. Dynamic gate stress is addressing this issue by applying switching cycles to the gate. Drain-source is commonly shorted during the stress phase. However, according to AQG 324 this is only allowed if there is no influence of a drain-source bias on gate-source threshold voltage drift. This paper compares the drift with and without drain-source bias of several manufacturers in an H-bridge configuration.