Extending Verilator to Enable Fault Simulation

Inhalt:
Fault simulation is a technique used to evaluate the robustness of safety-critical systems. An objective of the technique is to inject faults into a system and to observe its behavior. To deal with the large and complex designs, fast and valid fault simulation techniques are highly demanded. For this purpose fault simulators are used. Fault simulators are software programs that facilitate fault injection on a design model and capture the responses of a design for different fault types. This paper explores methods for extending a hardware simulator with fault injection capability. We consider Verilator, an open source hardware simulator, for fault simulation of complex designs. Towards this end, we extend Verilator with fault injection capability. Verilator’s high performance combined with the added functionality for fault modeling provides accurate and fast results to measure the dependability and robustness of designs. To evaluate and validate the approach, different fault models were injected into several designs. The experimental results show an average slowdown of 23% of the simulator runtime. Furthermore, the technique was used to evaluate the dependability of an SoC with a safety related software flow monitoring algorithm.