Online verification of AMS Properties

Inhalt:
In this paper, we present a novel framework for simulative verification of analog VHDL-AMS components. The environment consists of a simulatable top level component written in VHDL-AMS, which instantiates a Device Under Test (DUT) with arbitrary analog inputs and outputs using a layer of abstraction. DUT verification is done by monitor modules during simulation runtime (online) using an external tool, which communicates with the simulation tool using a software library. This allows for monitors in arbitrary programming languages while dropping the necessity of saving simulation traces. Furthermore, we show how analog-extended PSL properties can be verified online.