Heterogeneous 3D Integration for Smart Systems
Konferenz: Mikrosystemtechnik 2013 - Von Bauelementen zu Systemen
14.10.2013 - 16.10.2013 in Aachen, Deutschland
Tagungsband: Mikrosystemtechnik 2013
Seiten: 4Sprache: EnglischTyp: PDF
Persönliche VDE-Mitglieder erhalten auf diesen Artikel 10% Rabatt
Autoren:
Wolf, Juergen; Lang, Klaus-Dieter (Fraunhofer IZM, ASSID Berlin, Dresden, Germany)
Inhalt:
According to the increasing application driven demands on functionality, performance, miniaturization and reliability for microelectronic systems, System in Packages (SiP) using 3D integration are key elements for advanced microelectronic packaging. Key elements for 3D wafer level SiPs are the formation of Through Silicon Vias (TSVs) and their process integration into active devices as well as silicon interposer as a key enabler for 3D Systems.