Design of a Low Noise Frequency-synthesizers for Digital Video Broadcasting-Handheld System

Inhalt:
In this work, The design of PLL frequency synthesizer for the digital video broadcasting-handheld (DVB-H) is proposed. A system study of a zero-IF dual band DVB-H tuner is described. To meet the required noise figure specification, a 3- order Σ–Δ| fractional-N PLL is adopted to cover UHF band and L band. At last, the design and implementation of key circuits in the PLL loop is presented. A wideband VCO can be employed which covers a range of frequency 1.5 to 1.8 GHz. The synthesizer which implemented in 0.18 um CMOS achieved a low phase noise with -126 dBc/Hz @ 1MHz frequency offset in simulation. Index Terms — Digital video broadcasting-handheld (DVB-H), dual modulus prescalers, phase-locked loops (PLLs), extended true single phase clock logic (ETSPC).