Rubric: Proceedings - General Proceedings
DVCon Europe 2023
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DVCon Europe (Ed.)

New Book!

DVCon Europe 2023

Design and Verification Conference and Exhibition November 14-15, 2023 in Munich, Germany

2023, 93 pages, 140 x 124 mm, Slimlinebox, CD-Rom
ISBN 978-3-8007-6205-7, e-book: ISBN 978-3-8007-6206-4
Personal VDE Members are entitled to a 10% discount on this title

Content Foreword

The Design and Verification Conference in Europe (DVCon Europe) is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits.

DVCon Europe brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.
DVCon Europe organizes technical workshops and tutorials on emerging EDA and IP standards, with highly educational content. Experts in the industry share on topics like UVM, SystemC and IP-XACT, with the fundamental concepts and practical usage of these standards explained, including examples and demonstrations.
Search Conference Papers
1

Variation-Aware Performance Verification of Analog Mixed-Signal Systems

Authors:
Zivkovic, Carna; Roedel, Jan; Chavan, Neha; Rethmeier, Frank; Grimm, Christoph
2

Clock Tree Design Considerations in The Presence of Asymmetric Transistor Aging

Authors:
Gabbay, Freddy; Ramadan, Firas; Ganaiem, Majd
3

On the Performance Differences of SystemC and SystemC AMS: A Guideline for Real Number Modeling and Beyond

Authors:
Kuester, Alexandra; Dorsch, Rainer; Haubelt, Christian
4

A Tool for Investigating Cyber-Physical Systems via SystemC AMS Virtual Prototypes Derived from SysML Models

Authors:
Genius, Daniela; Apvrille, Ludovic
5

DSA Monitoring Framework for HW/SW Partitioning of Application Kernels leveraging VPs

Authors:
Hazott, Christoph; Grosse, Daniel
6

Co-Design of Automotive Boardnet Topology and Architecture

Authors:
Post, Sebastian; Grimm, Christoph
7

MapGL: Interactive Application Mapping and Profiling on a Grid of Processing Cells

Authors:
Raccomandato, Claudio; Arasteh, Emad M.; Doemer, Rainer
8

Evaluation of the RISC-V Floating Point Extensions

Authors:
Zurstrassen, Niko; Reimann, Lennart M.; Bosbach, Nils; Juenger, Lukas; Leupers, Rainer
9

Control Flow Analysis for Bottom-up Portable Models Creation

Authors:
Bardonek, Petr; Zachariasova, Marcela
10

A Compositional Simulation Framework for Testing Adversarial Robustness of Deep Neural Networks

Authors:
Maher Nader, Youssef; Lotfy Hatab, Mostafa; Ghaleb, Mazen Mostafa; Bakr, Safia Medhat; Awaad, Tasneem A.; AlGanzouri, Ahmed; Abdelsalam, Mohamed; Watheq El-Kharashi, M.
11

MetaPSS: An Automation Framework for Generation of Portable Stimulus Model

Authors:
Nagar, Jaimini; Dworzak, Thorsten; Simon, Sebastian; Heinkel, Ulrich; Lettnin, Djones
12

Large-scale Gatelevel Optimization Leveraging Property Checking

Authors:
Klemmer, Lucas; Bonora, Dominik; Grosse, Daniel