Characterization of a Power-Hardware-in-the-Loop Testbed Including Time Delays

Abstract:
Power-Hardware-in-the-Loop (PHiL) simulations enhance testbeds used for demonstration of power electronics components and DC system interactions which are of use in future on-board supplies and power systems, by interfacing real-time simulated models and actual hardware with power amplifiers. For modelling purposes, stability analysis, and interface design, it is essential to fully characterize the PHiL testbed with its components. Especially the connection between discrete simulation and actual hardware together with time delays could negatively affect the stability regions of the setups. In this paper, a method for characterizing the PHiL testbed including time delays with simple experiments and assumptions is presented and validated by designing an interface for an otherwise unstable test case.