Stability Improvement of a Dynamic Low-Voltage Power Hardware-in-the-Loop Environment

Abstract:
Power hardware-in-the-loop (PHIL) makes it possible to study the behavior between real hardware-under-test (HuT) and a virtual environment under safe laboratory conditions. New control methods for inverters or their behavior on power grids can thus be examined without disturbing real grid operation. However, the realistic simulations can become unstable if the impedances of the simulation and the HuT do not have the correct ratio. Although feedback signal filters (FSF) implemented in software can improve stability, they reduce the accuracy of the system. The correct setting of the cut-off frequency is therefore essential. Due to inductances in the simulation, numerical oscillations can also occur when the state variables change abruptly. This is caused by the trapezoidal rule implemented in the real-time converters for solving the differential equations in the simulation. This contribution demonstrates these challenges in an experimental PHIL labor-atory setup using realistic grid scenarios and analyzes the signals in the time and frequency domain. The setup consists of a solar emulator and a benchmark low voltage (LV) grid, which are simulated in real-time. A real solar inverter is used as HuT. This paper presents a method for controlling the cut-off frequency of the FSF after topology changes in the LV grid, depending on the high-frequency signal components which occur in the unstable state. In addition, a low-voltage ride through (LVRT) scenario is used to show how the numerical oscillations are compensated by implementing a numerical stabilizer.