Research on Electrical Characteristics of 1200V SiC Trench MOSFET with Periodic Arrangement of 3D P-shield Structure

Abstract:
In this study, we developed a 1200V SiC trench gate MOSFET device by utilizing ion implantation to create periodic P-type shielding structure in the trench, this approach significantly reduces the electric field stress on the trench gate oxide layer, with a peak electric field below 2MV/cm under a blocking voltage of 1200V. Additionally, we examined the effects of the H2 annealing process on trench sidewall roughness and the restoration of lattice damage at SiC/SiO2 interfaces through high-temperature annealing. By optimizing the process, we attained a sidewall roughness of 0.11nm and a channel field-effect mobility of 51.6cm2/V·s, thereby enhancing the device's dynamic-static and robustness trade-off. Ultimately, utilizing L5 series packaging, we assessed the chip's performance, achieving a RDSON of less than 10milliohm and an ESC over 13J.