Comprehensive Board Level Temperature Cycling Lifetime Projection of WLCSP GaN Power Devices

Abstract:
Wafer level chip scale packaged (WLCSP) gallium nitride (GaN) power devices have been deployed in increasingly advanced applications that demand high board-level temperature cycling (TC) reliability. In this study, a comprehensive TC lifetime model is developed, accounting for different device sizes and varying land grid array (LGA) solder bump dimensions. COMSOL finite element analysis (FEA) simulations were conducted to model the characteristic TC lifetime based on solder fatigue wear-out mechanism. The simulated results agree with the experi-mental data, validating the proposed TC lifetime model.