Σ-Δ based Current Acquisition with Reduced Settling Time

Abstract:
An approach of σ-δ (Σ Δ) based current acquisition with reduced settling time of the digital decimation filter and/or an increase of the effective number of bits (ENOB) is presented. Additionally, short circuits are also faster detectable. This is achieved by digitally compensating for the known parasitic inductance of the current sense shunt. The required digital signal processing can be performed by an FPGA or processor-based. This proposed method is compared to the commonly used sinc³ filter approach.