Modulation Technique for Reduced AC Content of the DC Link Current in Three-Phase Two-Level Inverters

Abstract:
DC link capacitor lifetime plays a crucial role in the design of power inverters. One of the main contributors to capacitor aging is the operation at high temperatures which comes with high capacitor currents. While higher switching frequencies allow for a down-sizing of the DC link capacitance, the required current rating is unaffected. To counteract this, a modulation technique is presented that reduces the DC current ripple significantly. Furthermore, the effects on DC bus current ripple, DC bus voltage ripple, output voltage quality and switching losses are evaluated based on simulations.