High Temperature Experimental Characterizations of COSS of 3.3 kV SiC MOSFET for Medium Voltage PV Applications

Abstract:
The rapid development of Wide Band Gap semi-conductors (WBG) in medium voltage area (MV) contributes to the enhancement and the integration of power electronics on the electrical power grid. Indeed, high frequency systems become crucial for any MVDC implementation. Then, the losses mechanism of the entire system requires an accurate investigation in order to design high performant equipment. Focusing on the power switches, semi-conductors include switching losses and conduction losses, which can be determined by conventional methods. In Metal-Oxide Semiconductor Field-Effect Transistors (MOSFETs), switching losses rely directly on the output capacitance (COSS), which is the sum of the Drain-Source capacitance (CDS) and the Drain-Gate capacitance (CDG). Therefore, at every switching cycle the output capacitance is discharged conducting to additional power dissipation. Moreover, for soft switching configuration, the output capacitance can be a key element in the design of ZVS or ZCS topologies, as in DC-DC Phase-Shifted Full Bridge converter. Thus, parasitic elements, including C(OSS) capacitance, are usually identified using static characterization methods. In this article, the extracted measurements from Silicon Carbide (SiC) MOSFETs are revised by two dynamic characterization methods. Besides, high temperature static measurement have been carried out using an automatic industrial equipment the Keysight B1506A, coupled with a ThermoStream. Concerning experimental measurements, this paper presents one direct practical technic and an applied resonant method in order to identify the output capacitance of medium voltage SiC transistors. This work employs discreet 3.3 kV/11 A (400 mOmega) SiC MOSFETs in a TO-247-4-lead package while the measurements take into account the parasitic elements of the circuit.