Analysis and Optimization of Internal Coupling Interference in Integrated SiC Power Module Based on DBC

Abstract:
Silicon carbide devices have higher switching speeds than traditional silicon-based devices and can operate at higher switching frequencies. The packaging structure of the integrated gate driver can significantly reduce the parasitic inductance in the drive circuit, reduce the drive resistance value, and increase the switching speed of SiC devices. Integrating the driver on the DBC can further improve the integration and heat dissipation of the driver chip. However, due to the shared DBC, the dv/dt during the switching process will be coupled to the signal input side of the driver chip through the parasitic capacitance between DBC layers, causing interference. The existing analysis of this phenomenon has problems such as incomplete consideration of parameters and the introduction of redundant parameters, and the accuracy is not high. This paper establishes a coupling interference model that considers the complete parasitic parameters in the DBC integrated power module, and proposes an optimized structure of the copper layer at the bottom of the DBC based on this model. The experimental results show that the proposed improved coupling interference model has high accuracy, and the calculation The error is within 8%. At the same time, the optimized structure of the copper layer at the bottom of the DBC proposed can increase the switching speed of the integrated SiC power module by more than 50%.