Power Cycling Reliability and Failure Mode Analysis of POL

Abstract:
Power Overlay (POL) is a power semiconductor package that utilizes advantages of wide bandgap semiconductors. POL has Copper (Cu) wiring formed on a polyimide substrate and Cu vias joining the topside of devices. In this paper, we investigated the reliability results and failure mode analysis of POL in a power cycling test. Further, we studied the correlation between remaining joint area and reliability on power cycling test using finite element method (FEM) simulation. The failure mode of POL is crack between Cu vias and electrodes of top side of power devices. We have found that even if the Cu via joining area was less than 40%, the electrical and thermal resistance increase were minor. The FEM results also showed that the characteristics degradation in a power cycling test are minor even if the Cu via joining area is reduced, and that the solder joining area on the bottom side of the devices is dominant. These results demonstrate that Cu via joining, a feature of POL, have high power cycling reliability.