Reconfigurable Double Pulse Test Setup for Si and Wide Bandgap Power FETs

Abstract:
The design of a low parasitic and user-friendly double pulse test (DPT) printed circuit board (PCB) is discussed to analyse the capacitances of a discrete power FET. To measure the drain current of the FET accurately, a surface-mount coaxial shunt resistor is added to the design. To facilitate the testing process, a mother-daughter PCB configuration is added. A parasitic analysis is performed to check whether the configuration can lead to signal distortion. The results indicate that distortion occurs for frequencies above 10MHz, much higher than the intended frequency, so the mother-daughter design has no impact on the results. The turn-on and turn-off transients of different DPT tests were captured. The switching times, parasitic capacitances and gate chargers were determined from the measured waveforms. The results demonstrated that although significantly higher, the measured capacitance follows the same trend. The measured switching times and gate charges differ slightly from the provided datasheet. This is due to the different test conditions used for the datasheet.