Gate-Driver Design and Optimization in Power Converters

Abstract:
In recent years, the adoption of new topologies and modern power switches supported improvements of power converters for high performance. Researchers and designers are often confronted with multiple variables to achieve one key design goal: reliable converters with high efficiency. In particular, challenges arise in the process of fine-tuning the converter to achieve extremely competitive performance levels with high reliability. This paper explores the issues of modulator and unsupervised gatedrivers design which can lead to unexpected faulty behavior in operation of power converters. Gatedriving circuits have been investigated and fine-tuned to eliminate the potential skipping pulses or malfunctions of the driving signals. Furthermore, the paper investigates and proposes a gate-driver design that maintains stable and safe operation of the power converters. The design improvements have been implemented in half-bridge and three-phase 3L-TNPC converter topologies. A modulation technique has been presented to limit the minimum duty-cycles in 3L-TNPC converters. The short pulses at the gate level are unable to fully turn-on de power devices, which can result in extra losses while power conversion transfer has not been achieved.