Open Loop Approach to Balance Cross-Currents in Time Staggered Switching SiC-Converters

Abstract:
The effects of steep voltage slopes caused by fast switching semiconductors include over voltages at long cables and capacitive bearing currents. With the utilisation of wide bandgap (WBG) semiconductors with their very high switching speed and possible switching frequency, the problem becomes even more urgent. Losses of state of the art solutions with clamped dv/dt filters increase relevantly. This contradicts the most outstanding advantage of WBG-semiconductors. An alternative filter topology using an interphase transformer with two paralleled half-bridges per phase avoids most of the losses. However, cross-current within the interphase transformer, mainly caused by blanking time effects, drives the interphase transformer into saturation if no countermeasures are taken. Previous approaches to limit the cross-current are based on closed-loop control, involving suitable measuring devices. This paper presents a new low-effort solution, based on an open-loop control without the need of measurement. The associated control is described in detail, including its implementation. Verification is achieved by measurements taken at a 500 kVA SiC-converter testbench.