Adder design of three N-bit binary numbers based on hybrid Memristor-NMOS

Abstract:
The switching characteristics of memristor make it have a good application prospect in digital logic. In recent years, researchers have proposed many memristor-based adder and multiplier logic circuit designs. It can realize the sum operation of multi-bit binary numbers of 2 numbers. However, when encountering an operation of three or more numbers, it is necessary to add two by two, and then add them again, which is time-consuming and wastes hardware resources. Based on this, this paper designs an adder circuit with three n-bit binary numbers, which can realize the sum operation of multiple inputs. Compared with the traditional adder circuit, it not only reduces the expenditure of hardware resources, but also reduces the delay Time.