Research on Comparator Design with Low Power Consumption and Improved Delay

Abstract:
This paper introduces three new comparator designs and their advanced performance. The entire effective transconductance of the latch stage mainly determine the delay of the comparator. The latch stage uses separated gate-biasing cross-coupled transistors, which increases its effective entire transconductance simultaneously, and leads to lower delay and energy consumption. A latch comparator with a dynamic pre-amp is designed to optimize power consumption. Compared to the traditional design, this dynamic one saves the extra power consumption when discharging to ground. But it deteriorates the circuit delay. The Double-Tail latch-type comparator solves low power supply problem by cascading the input stage and latch. In order to further improve the delay performance, three latches cascading is applied, combining with parallel feedforward paths.