The Overview of optimization methods in comparator design

Abstract:
This paper has introduced and analyzed the design methodology of four advanced comparator architectures. A SA-base comparator with N-additional discharging paths is proposed by Siddharth R.K., which can lower the delay by 50% comparing with the conventional SA comparator. The comparator proposed by Bernhard Goll has achieved low supply voltage (0.65V) application by expanding the comparator’s latch into two paths. Another advanced comparator is proposed by Xiyuan Tang, which achieves high energy efficiency. A floating reservoir capacitor is adopted as the energy supply of the input pairs in this comparator’s pre-amplifier stage. This comparator achieves a greater than seven-time improvement on energy efficiency over the classic one. Additionally, an architecture consisting of a PMOS latch, PMOS pre-amplifier with a cross-coupled circuit is proposed by Ata Khorami. It leads to a low-power, high-speed comparator which provides about 30% improvement of speed and reduces 50% power consumption.