Design Analysis of Dynamic Comparator

Abstract:
This paper covers four comparators with new-designed structures, each of them having superior performance than the classic comparators. A novel comparator design with parallel signal pathways to the output node boosts the comparator's transconductance and reduces voltage offset and overall latency in comparison to the conventional circuit. Similarly, A distinctive latching-stage design based on a gate-biasing cross-coupled material further optimizes the delay and power consumption of the comparator by increasing the overall transconductance of transistors. Meanwhile, a unique Triple- Tail (TT) fully dynamic comparator applies two preamplifiers in series with the latching stage, minimizes the total resolving time of the comparator and further raises the sampling rate without increasing input-referred noise and energy usage. Lastly, Edge-Pursuit Comparator (EPC) combines a non-coincident gate and an inverting delay unit, which leads two input signals chase each other in a ring oscillator to give a comparison result. The circuit construction provides flexible input noise, automatic energy scaling, and low voltage tolerance.