Analysis of Thermal Stress in Three Dimensional Package
Conference: ISCTT 2021 - 6th International Conference on Information Science, Computer Technology and Transportation
11/26/2021 - 11/28/2021 at Xishuangbanna, China
Proceedings: ISCTT 2021
Pages: 4Language: englishTyp: PDF
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Authors:
Jiang, Han; Zhu, Zhiyuan (College of Electronic and Information Engineering, Southwest University, Chongqing, China)
Gan, Hua (Science and Technology on Electronic Information Control Laboratory, Chengdu, China)
Zhang, Hongze (Nanjing Electronic Device Institute, Nanjing, China)
Abstract:
The maturity of TSV technology enabled the rapid development of 3D integration, enabling it to meet higher performance requirements. However, the operation of high-performance active devices would increase the temperature of chip, which cause great thermal stress inside the chip due to great mismatch CTE (Coefficient of thermal expansion) of materials. Therefore, how to depress the thermal stress of three-dimensional package was a critical problem. In this work, the new structure of three-dimensional package was proposed to analyze the variety of thermal stress. Compare with traditional 3-D package, the new structure could reduce thermal stress. On this basis, the situation occurred peak thermal stress of 3-D package was discussed. At same time, the deformation of 60Sn-40Pb solider ball and under bump metallization (UBM) was be extensive analysis in normal working temperature. The thermal stress and deformation of three-dimensional package would be better guidance for high-performance active devices.