Simulation Based Design of Experiments of Power Cycling Tests using Die Top System Interconnect Technology Die Topy System (DTS(r))

Abstract:
Increasing requirements towards higher power density and reliability demand new interconnect solutions. The Die Top System (DTS(r), Heraeus Electronics) enables high reliable Cu bonding in combination with state-of the art die technologies based on Si or SiC, only precondition being a sinterable top side metallization of the chip. Suitable Diodes, IGBTs, MOSFETs or Thyristors have become standard products for many suppliers. The use of Cu wires prevents the otherwise common bond wire lift-off failure in Power Cycling Testing while the silver sintered die-substrate interconnection suppresses the degradation of the die attach interface layer. The occurring failure mechanisms using DTS(r) and Cu-bonding are degradation of the Al-front side metallization (Al-FSM) of the chip and partially degradation of the DTS(r) sinter layer. In order to understand the impact of geometrical design and material properties of components used in a power module on its power cycle reliability a simulation-based approach will be presented to analyze their respective impact on the failure mechanism. Results show that hardness of the Al-FSM is a crucial factor that primarily determines the lifetime of a given package design. Furthermore, the material of chip, baseplate, ceramic, DTS(r)-Cu thickness and hardness have high impact on module lifetime and could easily change it by a factor of 10. Using this knowledge, the simulation model allows to predict the lifetimes for different designs and load conditions in the design phase.