Design of Low-Resistance and Area-Efficient GaN-HEMTs for Low-Voltage Power Applications

Abstract:
This work analyzes different layouts for low-resistance and area-efficient GaN-HEMT devices for lowvoltage power applications. The current distribution in interdigital comb and matrix structures is investigated and geometry parameters are optimized to achieve the lowest possible area-specific onstate resistance for given technology limits. A new model is analytically derived to investigate the static on-state behavior in matrix structures. Fabricated large area power transistors feature low specific onstate resistances RON∙A of 0.61 mOmega∙cm2 for the comb structure, a reduced specific on-state resistance of 0.37 mOmega∙cm2 for the matrix structure, and a further reduced specific onstate resistance of 0.23 mOmega∙cm2 for a high-density, fully symmetrical matrix structure.