Packaging for multi-die integration of GaN transistors in application under 1kW

Abstract:
Monolithic integration of GaN power transistors is considered as the ultimate implementation. Indeed, it minimizes the parasitic inductances while reducing the die area. However, the shared silicon substrate is at the origin of parasitic effects which result in higher losses. Although recent works highlight some solutions, they lead to processes that are more complex. As an alternative, this study proposes to use a printed circuit board embedded die package to compete with the monolithic solution. Thermal and parasitic aspects are investigated. This paper demonstrates that this level of integration is well suited for applications under 1kW without complex backside process.