A Current Hysteresis Controller for Reduction of Switching Losses in a Full-Bridge Inverter - FPGA implementation by using a custom developed 24 bit Floating Point Math Library
Conference: UPEC 2011 - 46th International Universities' Power Engineering Conference
09/05/2011 - 09/08/2011 at Soest, Germany
Proceedings: UPEC 2011
Pages: 6Language: englishTyp: PDF
Personal VDE Members are entitled to a 10% discount on this title
Authors:
Miglionic, M. C. (Department of Culture of the Project Second University of Naples, Via S. Lorenzo, Monastero di San Lorenzo, 81031 Aversa (CE), Italy)
Parillo, F. (Department of Automation, Electromagnetism, Computer Science and Industrial Mathematics, University of Cassino, Via G. Di Biasio 43, 03043 Cassino (FR), Italy)
Abstract:
This work explores the feasibility of implementing IEEE 754 standard compliant, 24 bit floating point unit on reconfigurable computing systems. The floating point unit generation approach outlined in this paper allows the creation of a vast collection of floating point routines. The developed library has been tested by means a proposed hybrid current hysteresis strategy control for the reduction of the switching losses in a full bridge inverter. The proposed hysteresis current controller is compared with the conventional one. Simulated and experimental results are included to show the effectiveness of the proposed current controller and the today's FPGA devices are well suited for this operation also by using a low cost device.